Rainbow Electronics DS3134 - Manual (Page 116)

DS3134
116 of 203
Bit 4 / Receive Done Queue FIFO Enable (RDQFE). To enable the DMA to burst write descriptors to
the Done Queue; this bit must be set to a one. If this bit is set to zero, messages will be written one at a
time.
0 = Done Queue Burst Write Disabled
1 = Done Queue Burst Write Enabled
Bit 5 / Receive Done Queue FIFO Flush (RDQF). When this bit is set to one, the internal Done Queue
FIFO will be flushed by sending all data into the Done Queue. This bit must be set to zero for proper
operation.
0 = FIFO in normal operation
1 = FIFO is flushed
Bits 8 to 10 / Receive Done Queue Status Bit Threshold Setting (RDQT0 to RDQT2). These 3 bits
determine when the DMA will set the Receive DMA Done Queue Write (RDQW) status bit in the Status
Register for DMA (SDMA) register.
000 = set the RDQW status bit after each descriptor write to the Done Queue
001 = set the RDQW status bit after 2 or more descriptors are written to the Done Queue
010 = set the RDQW status bit after 4 or more descriptors are written to the Done Queue
011 = set the RDQW status bit after 8 or more descriptors are written to the Done Queue
100 = set the RDQW status bit after 16 or more descriptors are written to the Done Queue
101 = set the RDQW status bit after 32 or more descriptors are written to the Done Queue
110 = set the RDQW status bit after 64 or more descriptors are written to the Done Queue
111 = set the RDQW status bit after 128 or more descriptors are written to the Done Queue
8.1.5 DMA CHANNEL CONFIGURATION RAM
Onboard the device there is a set of 768 dwords (3 dwords per channel times 256 channels) that are used
by the host to configure the DMA and by the DMA to store values locally when it is processing a packet.
Most of the fields within the DMA Configuration RAM are for use by the DMA and the Host will never
write to these fields. The Host is only allowed to write (i.e. configure) to the lower word of dword 2 for
each HDLC channel. The Host configurable fields are denoted with a thick box as shown below.