Rainbow Electronics DS3134 - Manual (Page 59)

DS3134
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Bit 6 / Sync Select Bit 0 (TSS0).
Bit 7 / Sync Select Bit 1 (TSS1).
These 2 bits select the mode in which each port is to be operated. Each port can be configured to accept
24, 32, 64, or 128 DS0 channels at an 8 kHz rate. These bits are ignored if the port has been configured
to operate in an unchannelized fashion (TUEN = 1).
00 = T1 Mode (24 DS0 channels & 193 RC clocks in between TS sync signals)
01 = E1 Mode (32 DS0 channels & 256 RC clocks in between TS sync signals)
10 = 4.096 MHz Mode (64 DS0 channels & 512 RC clocks in between TS sync signals)
11 = 8.192 MHz Mode (128 DS0 channels & 1024 RC clocks in between TS sync signals)
Bit 8 / Port 0 High Speed Mode (TP0(1)HS). If enabled, the Port 0(1) Layer 1 State Machine logic is
defeated and TC0(1) and TD0(1) are routed to some dedicated high speed HDLC processing logic. Only
present in TP0CR and TP1CR. Bit 8 is not assigned in Ports 2 through 15.
0 = disabled
1 = enabled
Bit 9 / Unchannelized Enable (TUEN). When enabled, this bit forces the port to operate in an
unchannelized fashion. When disabled, the port will operate in a channelized mode. This bit overrides
the Transmit Channel Enable (TCHEN) bit in the Transmit Layer 1 Configuration (T[n]CFG[j]) registers
which are described in Section 5.3.
0 = channelized mode
1 = unchannelized mode
Bit 10 / Unchannelized Network Loopback Enable (UNLB). See Figure 5.1A for details. This
loopback cannot be used for ports 0 & 1 when they are being operated at speeds greater than 10 MHz.
0 = loopback disabled
1 = loopback enabled
Bit 11 / Unchannelized BERT Select (TUBS). This bit is ignored if TUEN = 0. This bit overrides the
Transmit BERT (TBERT) bit in the Transmit Layer 1 Configuration (T[n]CFG[j]) registers which are
described in Section 5.3.
0 = source transmit data from the HDLC controller
1 = source transmit data from the BERT block
Bit 14 / Interrupt Enable for TCOFA (IETC).
0 = interrupt masked
1 = interrupt enabled
Bit 15 / COFA Status Bit (TCOFA). This latched read only status bit will be set if a Change Of Frame
Alignment is detected. A COFA is detected by sensing that a sync pulse has occurred during a clock
period that was not the first bit of the 193/256/512/1024 bit frame. This bit will be reset when read and it
will not be set again until another COFA has occurred.