2 packet descriptors, Receive descriptor address storage table 8.1.2a, Receive descriptor example figure 8.1.2a – Rainbow Electronics DS3134 User Manual
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8.1.2 PACKET DESCRIPTORS
In main memory resides a contiguous section up to 65,536 quad dwords that make up the Receive Packet
Descriptors. The Receive Packet Descriptors are aligned on a quad dword basis and can be placed
anywhere in the 32-bit address space via the Receive Descriptor Base Address (see Table 8.1.2A).
Associated with each descriptor is a data buffer. The data buffer can be up to 8191 bytes long and must
be a contiguous section of main memory. The host can set two different data buffer sizes via the Receive
Large Buffer Size (RLBS) and the Receive Small Buffer Size (RSBS) registers (see Section 8.1.1). If an
incoming packet requires more space than the data buffer allows, then Packet Descriptors will be link-
listed together by the DMA to provide a chain of data buffers. Figure 8.1.2A is an example of how three
descriptors were linked together for an incoming packet on HDLC Channel 2. Figure 8.1.1A shows a
similar example. Channel 9 only required a single data buffer and hence only one Packet Descriptor was
used.
Packet Descriptors can be either free (i.e. available for use by the DMA) or used (i.e. currently contain
data that needs to be processed by the host). Free Packet Descriptors are pointed to by the Free Queue
Descriptors and used Packet Descriptors are pointed to by the Done Queue Descriptors.
Receive Descriptor Address Storage Table 8.1.2A
Register Name
Acronym
Address
Receive Descriptor Base Address 0 (lower word)
RDBA0
0750h
Receive Descriptor Base Address 1 (upper word)
RDBA1
0754h
Receive Descriptor Example Figure 8.1.2A
Free Descriptor
Base + 00h
Channel 2 First Buffer Descriptor
Base + 10h
Base + 20h
Free Descriptor
Base + 30h
Free Descriptor
Base + 40h
Base + 50h
Free Descriptor
Base + 60h
Base + 70h
Free Descriptor
Base + 80h
Free Descriptor
Base + FFFD0h
Free Descriptor
Base + FFFF0h
Channel 9 Single Buffer Descriptor
Channel 2 Second Buffer Descriptor
Channel 2 Last Buffer Descriptor
Free Queue Descriptor Address
Done Queue Descriptor Pointer
Maximum of 65536
Descriptors