Rainbow Electronics DS3134 - Manual (Page 172)

DS3134
172 of 203
Figure 10.3B
16-Bit Write Cycle
Intel Mode (LIM = 0)
Arbitration Enabled (LARBE = 1)
Bus Transaction Time = 4 LCLK (LRDY = 0100)
An attempted access by the Host causes the Local Bus to request the bus. If bus access has not been
granted (LBGACK* deasserted), then the timing shown at the top of the page will occur with LHOLD
being asserted and then once LHLDA is detected, the Local Bus will grab the bus for 32 to 1048576
clocks and then release it. If the bus has already been granted (LBGACK* asserted), then the timing
shown at the bottom of the page will occur.
Note: LA / LD / LBHE* / LWR* / LRD* are tri-stated.
LCLK
LHOLD
LHLDA
LBGACK*
32 to 1048576 LCLKs
lb_pi
LA[19:0]
LD[7:0]
LD[15:8]
LRD*
LWR*
Address Valid
LBHE*
Data Valid
Data Valid
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
LCLK
1 2 3 4