Rainbow Electronics DS3134 - Manual (Page 154)

DS3134
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Bit 25 & 26 / Device Timing Select Bits 0 & 1 (DTS0 & DTS1). These two read only bits are forced to
01b by the device to indicate that it is capable of the medium timing requirements for the PDEVSEL*
signal.
Bit 27 / Target Abort Initiated (TABT). This read only bit is forced to zero by the device since it will
not terminate a bus transaction with a target abort when the device is a target.
Bit 28 / Target Abort Detected by Master (TABTM). This read/write bit will be set to a one when the
device is a bus master and it detects that a bus transaction has been aborted by the target with a target
abort. This bit can be reset (set to zero) by the Host by writing a one to this bit.
Bit 29 / Master Abort (MABT). This read/write bit will be set to a one when the device is a bus master
and the bus transaction is terminated with a master abort (except for Special Cycle). This bit can be reset
(set to zero) by the Host by writing a one to this bit.
Bit 30 / PCI System Error Reported (PSE). This read/write bit will be set to a one when the device
asserts the PSERR* signal (even if it is disabled via the PSEC Command bit). This bit can be reset (set to
zero) by the Host by writing a one to this bit.
Bit 31 / PCI Parity Error Reported (PPE). This read/write bit will be set to a one when the device
detects a parity error (even if parity is disabled via the PARC Command bit). This bit can be reset (set to
zero) by the Host by writing a one to this bit.
Register Name: PRCC0
Register Description: PCI Revision ID / Class Code Register 0
Register Address:
0x008h
lsb
Revision ID (Read Only / set to 00h)
Class Code (Read Only / set to 00h)
Class Code (Read Only / set to 80h)
msb
Class Code (Read Only / set to 02h)
Bits 0 to 7 / Revision ID. These read only bits identify the specific device revision and are selected by
Dallas Semiconductor.
Bits 8 to 15 / Class Code Interface. These read only bits identify the sub-class interface value for the
device and are fixed at 00h. See Appendix D of PCI Local Bus Specification Revision 2.1 for details.
Bits 16 to 23 / Class Code Sub-Class. These read only bits identify the sub-class value for the device
and are fixed at 80h, which indicate "Other Network Controller". See Appendix D of PCI Local Bus
Specification Revision 2.1 for details.