Rainbow Electronics DS3134 - Manual (Page 76)

DS3134
76 of 203
Bits 0 to 31 / BERT 32-Bit Bit Counter (BERTBC0 and BERTBC1). This 32-bit counter will
increment for each data bit (i.e. clock) received. This counter is not disabled when the receive BERT
loses synchronization. This counter will be loaded with the current bit count value when the LC control
bit in the BERTC0 register is toggled from a low (0) to a high (1). When full, this counter will saturate
and set the BBCO status bit.
Register Name: BERTEC0
Register Description: BERT 24-Bit Error Counter (lower) & Status Information
Register Address:
0518h
7 6 5 4 3 2 1 0
n/a RA1 RA0 RLOS BED BBCO BECO SYNC
15 14 13 12 11 10 9 8
BERT 24-Bit Error Counter (lower byte)
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Real Time Synchronization Status (SYNC). Real time status of the synchronizer (this bit is not
latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared
when 6 or more bits out of 64 are received in error.
Bit 1 / BERT Error Counter Overflow (BECO). A latched bit which is set when the 24-bit BERT
Error Counter (BEC) overflows. Cleared when read and will not be set again until another overflow
occurs.
Bit 2 / BERT Bit Counter Overflow (BBCO). A latched bit which is set when the 32-bit BERT Bit
Counter (BBC) overflows. Cleared when read and will not be set again until another overflow occurs.
Bit 3 / Bit Error Detected (BED). A latched bit which is set when a bit error is detected. The receive
BERT must be in synchronization for it detect bit errors. Cleared when read.
Bit 4 / Receive Loss Of Synchronization (RLOS). A latched bit which is set whenever the receive
BERT begins searching for a pattern. Once synchronization is achieved, this bit will remain set until
read.
Bit 5 / Receive All Zeros (RA0). A latched bit which is set when 31 consecutive zeros are received.
Allowed to be cleared once a one is received.
Bit 6 / Receive All Ones (RA1). A latched bit which is set when 31 consecutive ones are received.
Allowed to be cleared once a zero is received.
Bits 8 to 15 / BERT 24-Bit Error Counter (BEC). Lower word of the 24-bit error counter. See the
BERTEC1 register description for details.