Rainbow Electronics DS3134 - Manual (Page 139)

DS3134
139 of 203
Register Name: TDQFFT
Register Description: Transmit Done Queue FIFO Flush Timer
Register Address:
0844h
7 6 5 4 3 2 1 0
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
15 14 13 12 11 10 9 8
TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 15 / Transmit Done Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that
on system reset, the timer will be set to 0000h which is defined as an illegal setting. If the Receive Done
Queue FIFO is to be activated (TDQFE = 1), then the Host must first configure the timer to a proper state
and then set the TDQFE bit to one.
0000h = illegal setting
0001h = Timer Count Resets to 1
FFFFh = Timer Count Resets to 65536
Register Name: TDMAQ
Register Description: Transmit DMA Queues Control
Register Address:
0880h
7 6 5 4 3 2 1 0
n/a n/a n/a n/a TDQF TDQFE TPQF TPQFE
15 14 13 12 11 10 9 8
n/a n/a n/a n/a n/a TDQT2 TDQT1 TDQT0
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Transmit Pending Queue FIFO Enable (TPQFE). See Section 8.2.3 for details.
Bit 1 / Transmit Pending Queue FIFO Flush (TPQLF). See Section 8.2.3 for details.
Bit 3 / Transmit Done Queue FIFO Enable (TDQFE). To enable the DMA to burst write descriptors
to the Done Queue; this bit must be set to a one. If this bit is set to zero, descriptors will be written one at
a time.
0 = Done Queue Burst Write Disabled
1 = Done Queue Burst Write Enabled
Bit 4 / Transmit Done Queue FIFO Flush (TDQF). When this bit is set to one, the internal Done
Queue FIFO will be flushed by sending all data into the Done Queue. This bit must be set to zero for
proper operation.
0 = FIFO in normal operation
1 = FIFO is flushed