Rainbow Electronics DS3134 - Manual (Page 31)

DS3134
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Signal Name: PSERR*
Signal Description: PCI System Error
Signal Type: Output (open drain)
This active low signal reports any parity errors that occur during the address phase. PSERR* can be
enabled and disabled via the PCI Configuration Registers. This signal is updated on the rising edge of
PCLK.
Signal Name: PINTA*
Signal Description: PCI Interrupt
Signal Type: Output (open drain)
This active low (open drain) signal is asserted low asynchronously when the device is requesting attention
from the device driver. PINTA will be deasserted when the device interrupting source has been service or
masked. This signal is updated on the rising edge of PCLK.
PCI Extension Signals
These signals are not part of the normal PCI Bus signal set. There are additional signals that are asserted
when Chateau is an Initiator on the PCI Bus to help users interpret the normal PCI Bus signal set and
connect them to a non-PCI environment like an Intel i960 type bus. The timing for these signals is shown
below.
Signal Name:
PXAS*
Signal Description: PCI Extension Address Strobe
Signal Type: Output
This active low signal is asserted low on the same clock edge as PFRAME* and is deasserted after one
clock period. This signal will only be asserted when the device is an initiator. This signal is an output
and is updated on the rising edge of PCLK.
Signal Name: PXDS*
Signal Description: PCI Extension Data Strobe
Signal Type: Output
This active low signal is asserted when the PCI bus either contains valid data to be read from the device
or can accept valid data that is written into the device. This signal will only be asserted when the device
is an initiator. This signal is an output and is updated on the rising edge of PCLK.
Signal Name: PXBLAST*
Signal Description: PCI Extension Burst Last
Signal Type: Output
This active low signal is asserted on the same clock edge as PFRAME* is deasserted and is deasserted on
the same clock edge as PIRDY* is deasserted. This signal will only be asserted when the device is an
initiator. This signal is an output and is updated on the rising edge of PCLK.