Rainbow Electronics DS3134 - Manual (Page 81)

DS3134
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Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Receive HDLC Definition RAM, this bit should be written to a one by the host. This causes the device to
begin obtaining the data from the channel location indicated by the HCID bits. During the read access,
the IAB bit will be set to one. Once the data is ready to be read from the RHCD register, the IAB bit will
be set to zero. When the host wishes to write data to the internal Receive HDLC Definition RAM, this bit
should be written to a zero by the host. This causes the device to take the data that is current present in
the RHCD register and write it to the channel location indicated by the HCID bits. When the device has
completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
Register Name: RHCD
Register Description: Receive HDLC Channel Definition
Register Address:
0404h
7 6 5 4 3 2 1 0
RABTD RCS RBF RID RCRC1 RCRC0 ROLD RTRANS
15 14 13 12 11 10 9 8
n/a n/a n/a n/a n/a n/a n/a RZDD
Note: Bits that are underlined are read only, all other bits are read-write.
Bit 0 / Receive Transparent Enable (RTRANS). When this bit is set low, the HDLC engine performs
flag delineation, zero destuffing, abort detection, octet length checking (if enabled via ROLD), and FCS
checking (if enabled via RCRC0/1). When this bit is set high, the HDLC engine does not perform flag
delineation, zero destuffing, and abort detection, octet length checking, or FCS checking.
0 = transparent mode disabled
1 = transparent mode enabled
Bit 1 / Receive Octet Length Detection Enable (ROLD). When this bit is set low, the HDLC engine
does not check to see if the octet length of the received packets exceeds the count loaded into the Receive
HDLC Packet Length (RHPL) register. When this bit is set high, the HDLC engine checks to see if the
octet length of the received packets exceeds the count loaded into the RHPL register. When an incoming
packet exceeds the maximum length, then the packet is aborted and the remainder is discarded. This bit is
ignored if the HDLC channel is set into Transparent mode (RTRANS = 1).
0 = octet length detection disabled
1 = octet length detection enabled