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Rainbow Electronics DS3134 User Manual

Page 163

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DS3134

163 of 203

SECTION 10: LOCAL BUS

10.1 LOCAL BUS GENERAL DESCRIPTION

The Local Bus can operate in two modes, as a PCI Bridge (master mode) and as a Configuration Bus
(slave mode). This selection is made in hardware by tying the LMS pin high or low. Figures 10.1A
through 10.1C describe the two modes. Figure 10.1A shows an example of the Local Bus being operated
in the PCI Bridge Mode. In this example, the Host can access the control ports on the T1/E1 devices via
the Local Bus.

Figure 10.1B also shows an example of the PCI Bridge Mode but in this example, the Local Bus
Arbitration is enabled which allows a Local CPU to control when the Host can have access to the Local
Bus. To access the Local Bus, the Host must first request the bus and then wait until it is granted.

Figure 10.1C displays an example of the Configuration Mode. In this mode, the CPU on the Local Bus
will configure and monitor the DS3134. In this mode, the Host on the PCI/Custom Bus cannot access the
DS3134 and the PCI/Custom Bus is only used to transfer HDLC packet data to and from the Host.

Table 10.1A lists all of the Local Bus pins and their application in both operating modes. The Local Bus
operates only in a non-multiplexed fashion; it is not capable of operating as a multiplexed bus. For both
operating modes, the Local Bus can be set up for either Intel or Motorola type busses. This selection is
made in hardware by tying the LIM pin high or low.

Local Bus Signals Table 10.1A

Signal Name

Signal Description

PCI Bridge Mode

(LMS = 0)

Configuration Mode

(LMS = 1)

LD[0:15]

Data Bus

Input on Read /

Output on Write

Input on Write /

Output on Read

LA[0:19]

Address Bus

Output

Input

LWR*(LR/W*)

Bus Write (Read/Write Select)

Output

Input

LRD*(LDS*)

Bus Read (Data Strobe)

Output

Input

LBHE*

Byte High Enable

Output

Tri-Stated

LIM

Intel/Motorola Select

Input

Input

LINT*

Interrupt

Input

Output

LMS

Mode Select

Input

Input

LCLK

Bus Clock

Output

Tri-Stated

LRDY*

Bus Ready

Input

Ignored

LCS*

Chip Select

Ignored

Input

LHOLD(LBR*)

Hold Request (Bus Request)

Output

Tri-Stated

LHLDA(LBG*)

Hold Acknowledge (Bus Grant)

Input

Ignored

LBGACK*

Bus Acknowledge

Output

Tri-Stated

Notes:
1. Signals shown in parenthesis () are active when Motorola Mode (LIM = 1) is selected.
2. Signals suffixed with an asterisk (*) are active low signals.