Rainbow Electronics DS3134 - Manual (Page 58)

DS3134
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Bit 15 / COFA Status Bit (RCOFA). This latched read only status bit will be set if a Change Of Frame
Alignment is detected. The COFA is detected by sensing that a sync pulse has occurred during a clock
period that was not the first bit of the 193/256/512/1024 bit frame. This bit will be reset when read and it
will not be set again until another COFA has occurred.
Transmit Side Control Bits (one each for all 16 ports)
Register Name: TP[n]CR where n = 0 to 15 for each Port
Register Description: Transmit Port [n] Control Register
Register Address:
See the Register Map in Section 3
7 6 5 4 3 2 1 0
TSS1 TSS0 TSD1 TSD0 TFDA1* TISE TIDE TICE
15 14 13 12 11 10 9 8
TCOFA IETC n/a n/a TUBS UNLB TUEN TP[i]HS
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Invert Clock Enable (TICE).
0 = do not invert clock (normal mode)
1 = invert clock (inverted clock mode)
Bit 1 / Invert Data Enable (TIDE).
0 = do not invert data (normal mode)
1 = invert data (inverted data mode)
Bit 2 / Invert Sync Enable (TISE).
0 = do not invert sync pulse (normal mode)
1 = invert sync pulse (inverted sync pulse mode)
Bit 3 / Force Data All 1's (TFDA1*).
0 = force all data at TD to be one
1 = allow data to be transmitted normally
Bit 4 / Sync Delay Bit 0 (TSD0).
Bit 5 / Sync Delay Bit 1 (TSD1).
These 2 bits define the format of the sync signal that will be applied to the TS[n] input. These bits are
ignored if the port has been configured to operate in an unchannelized fashion (TUEN = 1).
00 = sync pulse is 0 clocks early
01 = sync pulse is 1/2 clock early
10 = sync pulse is 1 clock early
11 = sync pulse is 2 clocks early