Rainbow Electronics DS3134 - Manual (Page 96)

DS3134
96 of 203
SECTION 8: DMA
8.0 INTRODUCTION
The DMA block (see Figure 1.1A) handles the transfer of packet data from the FIFO block to the PCI
block and vice versa. Throughout this Section, the terms Host and Descriptor will be used. Host is
defined as the CPU or intelligent controller that sits on the PCI Bus and instructs the device on how to
handle the incoming and outgoing packet data. Descriptor is defined as a pre-formatted message that is
passed from the Host to the DMA block or vice versa to indicate where packet data should be placed or
obtained from.
On power-up, the DMA will be disabled because the RDE and TDE control bits in the Master
Configuration register (see Section 4) will be set to zero. The Host must configure the DMA by writing
to all of the registers listed in Table 8.0A (which includes all 256 channel locations in the Receive and
Transmit Configuration RAMs) then enable the DMA by setting to the RDE and TDE control bits to one.
The structure of the DMA is such that the receive and transmit side descriptor address spaces can be
shared even among multiple chips on the same bus. Via the Master Control (MC) register, the Host will
determine how long the DMA will be allowed to burst onto the PCI bus. The default value is 32 dwords
(128 bytes) but via the RDT0/1 and TDT0/1 control bits, the Host can enable the receive or transmit
DMAs to burst either 64 dwords (256 bytes), 128 dwords (512 bytes), or 256 dwords (1024 bytes).
The receive and transmit Packet Descriptors have almost identical structures (see Sections 8.1.2 and
8.2.2) which provides a minimal amount of Host intervention in store-and-forward applications. In other
words, the receive descriptors created by the receive DMA can be used directly by the transmit DMA.
The receive and transmit portions of the DMA are completely independent and will be discussed
separately.