Rainbow Electronics DS3134 - Manual (Page 49)

DS3134
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Bit 11 / Status Bit for Receive DMA Done Queue Write Error (RDQWE). This status bit will be set
to a one each time the Receive DMA tries to write to the Done Queue and it is full. The RDQWE bit will
be cleared when read and will not be set again until another write to the Done Queue detects that it is full.
If enabled via the RDQWE bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will
cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local
Bus is in the Configuration Mode.
Bit 12 / Status Bit for Transmit FIFO Underflow (TUDFL). This status bit will be set to a one if any
of the HDLC channels experiences an underflow in the transmit FIFO. The TUDFL bit will be cleared
when read and will not be set again until another underflow has occurred. If enabled via the TUDFL bit
in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the
PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 13 / Status Bit for Transmit DMA Pending Queue Read (TPQR). This status bit will be set to a
one each time the Transmit DMA reads the Pending Queue. The TPQR bit will be cleared when read and
will not be set again until another read of the Pending Queue has occurred. If enabled via the TPQR bit in
the Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI
Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 14 / Status Bit for Transmit DMA Done Queue Write (TDQW). This status bit will be set to a one
when the Transmit DMA writes to the Done Queue. Based of the setting of the Transmit Done Queue
Threshold Setting (TDQT0 to TDQT2) bits in the Transmit DMA Queues Control (TDMAQ) register,
this bit will be set either after each write or after a programmable number of writes from 2 to 128. See
Section 8.2.4 for more details. The TDQW bit will be cleared when read and will not be set again until
another write to the Done Queue has occurred. If enabled via the TDQW bit in the Interrupt Mask for
SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA*
signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 15 / Status Bit for Transmit DMA Done Queue Write Error (TDQWE). This status bit will be set
to a one each time the Transmit DMA tries to write to the Done Queue and it is full. The TDQWE bit
will be cleared when read and will not be set again until another write to the Done Queue detects that it is
full. If enabled via the TDQWE bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will
cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local
Bus is in the Configuration Mode.