Rainbow Electronics DS3134 - Manual (Page 84)

DS3134
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Register Name: THCD
Register Description: Transmit HDLC Channel Definition
Register Address:
0484h
7 6 5 4 3 2 1 0
TABTE TCFCS TBF TID TCRC1 TCRC0 TIFS TTRANS
15 14 13 12 11 10 9 8
n/a n/a n/a TZSD TFG3 TFG2 TFG1 TFG0
Note: Bits that are underlined are read only, all other bits are read-write.
Bit 0 / Transmit Transparent Enable (TTRANS). When this bit is set low, the HDLC engine will
generate flags and the FCS (if enabled via TCRC0/1) and perform zero stuffing. When this bit is set high,
the HDLC engine does not generate flags or the FCS and does not perform zero stuffing.
0 = transparent mode disabled
1 = transparent mode enabled
Bit 1 / Transmit Interfill Select (TIFS).
0 = the interfill byte is 7Eh (01111110)
1 = the interfill byte is FFh (11111111)
Bit 2 & Bit 3 / Transmit CRC Selection (TCRC0/TCRC1). These 2 bits are ignored if the HDLC
channel is set into Transparent mode (TTRANS = 1).
TCRC1 TCRC0 Action
0 0 no CRC is generated
0 1 16-bit CRC (CCITT/ITU Q.921)
1 0 32-bit CRC
1 1 illegal state
Bit 4 / Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are
not inverted after being generated. When this bit is set high, the HDLC engine inverts all the data (flags,
information fields, and FCS) after the packet has been generated.
0 = do not invert data
1 = invert all data (including flags and FCS)
Bit 5 / Transmit Bit Flip (TBF). When this bit is set low, the HDLC engine will obtain the first HDLC
bit to be transmitted from the lowest bit position of the PCI Bus bytes (i.e. PAD[0] / PAD[8] / PAD[16] /
PAD[24]). When this bit is set high, the HDLC engine will obtain the first HDLC bit to be transmitted
from the highest bit position of the PCI Bus bytes (i.e. PAD[7] / PAD[15] / PAD[23] / PAD[31]).
0 = the first HDLC bit transmitted is obtained from the lowest bit position of the bytes on the
PCI Bus
1 = the first HDLC bit transmitted is obtained from the highest bit position of the bytes on the
PCI Bus