Samsung S3C2440A User Manual
Page 95
ARM INSTRUCTION SET
S3C2440A RISC MICROPROCESSOR
3-38
ASSEMBLER SYNTAX
LDR
Load from memory into a register
STR
Store from a register into memory
{cond}
Two-character condition mnemonic. See Table 3-2..
H
Transfer
halfword
quantity
SB
Load sign extended byte (Only valid for LDR)
SH
Load sign extended halfword (Only valid for LDR)
Rd
An expression evaluating to a valid register number.
can be:1
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the expression.
This will be a PC relative, pre-indexed address. If the address is out of range, an error will
be generated.
2
A pre-indexed addressing specification:
[Rn]
offset
of
zero
[Rn,<#expression>]{!}
offset
of
bytes
[Rn,{+/-}Rm]{!}
offset of +/- contents of index register
3
A post-indexed addressing specification:
[Rn],<#expression>
offset of
[Rn],{+/-}Rm
offset of +/- contents of index register.
4
Rn and Rm are expressions evaluating to a register number. If Rn is R15 then the
assembler will subtract 8 from the offset value to allow for ARM920T pipelining. In this
case base write-back should not be specified.
{!}
Writes back the base register (set the W bit) if ! is present.