Samsung S3C2440A - Manual (Page 284)

I/O PORTS S3C2440A RISC MICROPROCESSOR
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MSLCON (Memory Sleep Control Register)
Select memory interface status when in SLEEP mode.
Register Address R/W Description Reset Value
MSLCON 0x560000cc R/W Memory Sleep Control Register 0x0
MSLCON Bit Description Reset Value
PSC_DATA [11] DATA[31:0] pin status in Sleep mode.
0:
Hi-Z 1: Output “0”.
0
PSC_WAIT [10] nWAIT pin status in Sleep mode.
0: Input
1: Output “0”
0
PSC_RnB [9] RnB pin status in Sleep mode.
0: Input
1: Output “0”
0
PSC_NF [8] NAND Flash I/F pin status in Sleep
mode( nFCE,nFRE,nFWE,ALE,CLE).
0: inactive(nFCE,nFRE,nFWE,ALE,CLE = 11100)
1: Hi-Z 0
PSC_SDR [7] nSRAS, nSCAS pin status in Sleep mode.
0: inactive(“1”)
1: Hi-Z
0
PSC_DQM [6] DQM[3:0]/nWE[3:0] pin status in Sleep mode.
0: inactive
1: Hi-Z
0
PSC_OE [5] nOE pin status in Sleep mode.
0: inactive(“1”)
1: Hi-Z
0
PSC_WE [4] nWE pin status in Sleep mode.
0: inactive(“1”)
1: Hi-Z
0
PSC_GCS0 [3] nGCS[0] pin status in Sleep mode.
0: inactive(“1”)
1: Hi-Z
0
PSC_GCS51 [2] nGCS[5:1] pin status in Sleep mode.
0: inactive(“1”)
1: Hi-Z
0
PSC_GCS6 [1] nGCS[6] pin status in Sleep mode.
0: inactive(“1”)
1: Hi-Z
0
PSC_GCS7 [0] nGCS[7] pin status in Sleep mode.
0: inactive(“1”)
1: Hi-Z
0