Samsung S3C2440A - Manual (Page 243)

S3C2440A RISC MICROPROCESSOR DMA
8-11
DMA STATUS (DSTAT) REGISTER
Register Address R/W Description Reset Value
DSTAT0 0x4B000014 R DMA 0 count register 000000h
DSTAT1 0x4B000054 R DMA 1 count register 000000h
DSTAT2 0x4B000094 R DMA 2 count register 000000h
DSTAT3 0x4B0000D4 R DMA 3 count register 000000h
DSTATn Bit Description Initial State
STAT [21:20] Status of this DMA controller.
00: Indicates that DMA controller is ready for another DMA request.
01: Indicates that DMA controller is busy for transfers.
00b
CURR_TC [19:0] Current value of transfer count.
Note that transfer count is initially set to the value of DCONn[19:0]
register and decreased by one at the end of every atomic transfer.
00000h