Samsung S3C2440A - Manual (Page 205)

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR
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MAIN DATA AREA ECC0 STATUS REGISTER
Register Address R/W Description Reset Value
NFMECC0 0x4E00002C R NAND Flash ECC register for data[7:0] 0xXXXXXX
NFMECC1 0x4E000030 R NAND Flash ECC register for data[15:8] 0xXXXXXX
NFMECC0 Bit Description Initial State
MECC0_3 [31:24] ECC3 for data[7:0] 0xXX
MECC0_2 [23:16] ECC2 for data[7:0] 0xXX
MECC0_1 [15:8] ECC1 for data[7:0] 0xXX
MECC0_0 [7:0] ECC0 for data[7:0] 0xXX
NFMECC1 Bit Description Initial State
MECC1_3 [31:24] ECC3 data[15:8] 0xXX
MECC1_2 [23:16] ECC2 data[15:8] 0xXX
MECC1_1 [15:8] ECC1 data[15:8] 0xXX
MECC1_0 [7:0] ECC0 data[15:8] 0xXX
Note
The NAND flash controller generate NFMECC0/1 when read or write main area data while the
MainECCLock(NFCONT[5]) bit is ‘0’(Unlock).
SPARE AREA ECC STATUS REGISTER
Register Address R/W Description Reset Value
NFSECC 0x4E000034 R NAND Flash ECC register for I/O [15:0] 0xXXXXXX
NFSECC Bit Description Initial State
SECC1_1 [31:24] Spare area ECC1 Status for I/O[15:8] 0xXX
SECC1_0 [23:16] Spare area ECC0 Status for I/O[15:8] 0xXX
SECC0_1 [15:8] Spare area ECC1 Status for I/O[7:0] 0xXX
SECC0_0 [7:0] Spare area ECC0 Status for I/O[7:0] 0xXX
Note
The NAND flash controller generate NFSECC when read or write spare area data while the
SpareECCLock(NFCONT[6]) bit is ‘0’(Unlock).