Samsung S3C2440A - Manual (Page 272)

I/O PORTS S3C2440A RISC MICROPROCESSOR
9-26
DCLK CONTROL REGISTERS(DCLKCON)
Register Address R/W Description Reset Value
DCLKCON 0x56000084 R/W DCLK0/1 Control Register 0x0
DCLKCON Bit Description
DCLK1CMP [27:24] DCLK1 Compare value clock toggle value.( < DCLK1DIV)
If the DCLK1CMP is n, Low level duration is( n + 1),
High level duration is((DCLK1DIV + 1) –( n +1))
DCLK1DIV [23:20] DCLK1 Divde value
DCLK1 frequency = source clock /( DCLK1DIV + 1)
DCLK1SelCK [17] Select DCLK1 source clock
0 = PCLK
1 = UCLK( USB)
DCLK1EN [16] DCLK1 Enable
0 = DCLK1 disable 1 = DCLK1 enable
DCLK0CMP [11:8] DCLK0 Compare value clock toggle value.( < DCLK0DIV)
If the DCLK0CMP is n, Low level duration is( n + 1),
High level duration is((DCLK0DIV + 1) –( n +1))
DCLK0DIV [7:4] DCLK0 Divde value.
DCLK0 frequency = source clock /( DCLK0DIV + 1)
DCLK0SelCK [1] Select DCLK0 source clock
0 = PCLK
1 = UCLK( USB)
DCLK0EN [0] DCLK0 Enable
0 = DCLK0 disable 1 = DCLK0 enable
DCLKnDIV + 1
DCLKnCMP + 1