Samsung S3C2440A - Manual (Page 332)

USB DEVICE S3C2440A RISC MICROPROCESSOR
13-4
EP2_DMA_CON Endpoint2 DMA control register 0x218(L) / 0x21B(B)
EP2_DMA_UNIT Endpoint2 DMA unit counter register 0x21C(L) / 0x21F(B)
EP2_DMA_FIFO Endpoint2 DMA FIFO counter register 0x220(L) / 0x223(B)
EP2_DMA_TTC_L Endpoint2 DMA transfer counter low-byte register 0x224(L) / 0x227(B)
EP2_DMA_TTC_M Endpoint2 DMA transfer counter middle-byte register 0x228(L) / 0x22B(B)
EP2_DMA_TTC_H Endpoint2 DMA transfer counter high-byte register 0x22C(L) / 0x22F(B)
EP3_DMA_CON Endpoint3 DMA control register 0x240(L) / 0x243(B)
EP3_DMA_UNIT Endpoint3 DMA unit counter register 0x244(L) / 0x247(B)
EP3_DMA_FIFO Endpoint3 DMA FIFO counter register 0x248(L) / 0x24B(B)
EP3_DMA_TTC_L Endpoint3 DMA transfer counter low-byte register 0x24C(L) / 0x24F(B)
EP3_DMA_TTC_M Endpoint3 DMA transfer counter middle-byte register 0x250(L) / 0x253(B)
EP3_DMA_TTC_H Endpoint3 DMA transfer counter high-byte register 0x254(L) / 0x247(B)
EP4_DMA_CON Endpoint4 DMA control register 0x258(L) / 0x25B(B)
EP4_DMA_UNIT Endpoint4 DMA unit counter register 0x25C(L) / 0x25F(B)
EP4_DMA_FIFO Endpoint4 DMA FIFO counter register 0x260(L) / 0x263(B)
EP4_DMA_TTC_L Endpoint4 DMA transfer counter low-byte register 0x264(L) / 0x267(B)
EP4_DMA_TTC_M Endpoint4 DMA transfer counter middle-byte register 0x268(L) / 0x26B(B)
EP4_DMA_TTC_H Endpoint4 DMA transfer counter high-byte register 0x26C(L) / 0x26F(B)
COMMON INDEXED REGISTERS
MAXP_REG Endpoint MAX packet register 0x180(L) / 0x183(B)
IN INDEXED REGISTERS
IN_CSR1_REG/EP0_CSR EP In control status register 1/EP0 control status
register 0x184(L) / 0x187(B)
IN_CSR2_REG EP In control status register 2 0x188(L) / 0x18B(B)
OUT INDEXED REGISTERS
OUT_CSR1_REG EP out control status register 1 0x190(L) / 0x193(B)
OUT_CSR2_REG EP out control status register 2 0x194(L) / 0x197(B)
OUT_FIFO_CNT1_REG EP out write count register 1 0x198(L) / 0x19B(B)
OUT_FIFO_CNT2_REG EP out write count register 2 0x19C(L) / 0x19F(B)