Samsung S3C2440A - Manual (Page 78)

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET
3-21
ASSEMBLY SYNTAX
•••• MRS - transfer PSR contents to a register
MRS{cond} Rd,
•••• MSR - transfer register contents to PSR
MSR{cond} ,Rm
•••• MSR - transfer register contents to PSR flag bits only
MSR{cond} ,Rm
The most significant four bits of the register contents are written to the N,Z,C & V flags respectively.
•••• MSR - transfer immediate value to PSR flag bits only
MSR{cond} ,<#expression>
The expression should symbolise a 32 bit value of which the most significant four bits are written to the N,Z,C and
V flags respectively.
Key:
{cond} Two-character condition mnemonic. See Table 3-2..
Rd and Rm Expressions evaluating to a register number other than R15
CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR
and SPSR_all)
CPSR_flg or SPSR_flg
<#expression> Where this is used, the assembler will attempt to generate a shifted immediate 8-bit field
to match the expression. If this is impossible, it will give an error.
EXAMPLES
In User mode the instructions behave as follows:
MSR CPSR_all,Rm ; CPSR[31:28] <- Rm[31:28]
MSR CPSR_flg,Rm ; CPSR[31:28] <- Rm[31:28]
MSR CPSR_flg,#0xA0000000 ; CPSR[31:28] <- 0xA (set N,C; clear Z,V)
MRS Rd,CPSR ; Rd[31:0] <- CPSR[31:0]
In privileged modes the instructions behave as follows:
MSR CPSR_all,Rm ; CPSR[31:0] <- Rm[31:0]
MSR CPSR_flg,Rm ; CPSR[31:28] <- Rm[31:28]
MSR CPSR_flg,#0x50000000 ; CPSR[31:28] <- 0x5 (set Z,V; clear N,C)
MSR SPSR_all,Rm ; SPSR_[31:0]<- Rm[31:0]
MSR SPSR_flg,Rm ; SPSR_[31:28] <- Rm[31:28]
MSR SPSR_flg,#0xC0000000 ; SPSR_[31:28] <- 0xC (set N,Z; clear C,V)
MRS Rd,SPSR ; Rd[31:0] <- SPSR_[31:0]