Samsung S3C2440A - Manual (Page 107)

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR
3-50
ASSEMBLER SYNTAX
SWI{cond}
{cond} Two character condition mnemonic, Table 3-2.
Evaluated and placed in the comment field (which is ignored by ARM920T).
Examples
SWI ReadC ; Get next character from read stream.
SWI WriteI+"k” ; Output a "k" to the write stream.
SWINE 0 ; Conditionally call supervisor with 0 in comment field.
Supervisor code
The previous examples assume that suitable supervisor code exists, for instance:
0x08 B Supervisor ; SWI entry point
EntryTable ; Addresses of supervisor routines
DCD ZeroRtn
DCD ReadCRtn
DCD WriteIRtn
• • •
Zero EQU 0
ReadC EQU 256
WriteI EQU 512
Supervisor ; SWI has routine required in bits 8-23 and data (if any) in
; bits 0-7. Assumes R13_svc points to a suitable stack
STMFD R13,{R0-R2,R14} ; Save work registers and return address.
LDR R0,[R14,#-4] ; Get SWI instruction.
BIC R0,R0,#0xFF000000 ; Clear top 8 bits.
MOV R1,R0,LSR#8 ; Get routine offset.
ADR R2,EntryTable ; Get start address of entry table.
LDR R15,[R2,R1,LSL#2] ; Branch to appropriate routine.
WriteIRtn ; Enter with character in R0 bits 0-7.
• • •
LDMFD R13,{R0-R2,R15}^ ; Restore workspace and return,
; restoring processor mode and flags.