Samsung S3C2440A - Manual (Page 128)

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET
4-7
FORMAT 2: ADD/SUBTRACT
15
0
14 10
[2:0] Destination Register
[5:3] Source Register
[8:6] Register/Immediate Vale
[9] Opcode
0 = ADD
1 = SUB
[10] Immediate Flag
0 = Register operand
1 = Immediate oerand
Rn/Offset3 Rd 0 0
13 12 11
Op Rs
9 8
1 1 1
6 5 3 2 0
Figure 4-3. Format 2
OPERATION
These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from
a Lo register. The THUMB assembler syntax is shown in Table 4-3.
NOTE
All instructions in this group set the CPSR condition codes.
Table 4-3. Summary of Format 2 Instructions
OP I THUMB Assembler ARM Equipment Description
0 0 ADD Rd, Rs, Rn ADDS Rd, Rs, Rn Add contents of Rn to contents of Rs.
Place result in Rd.
0 1 ADD Rd, Rs, #Offset3 ADDS Rd, Rs, #Offset3 Add 3-bit immediate value to contents of
Rs. Place result in Rd.
1 0 SUB Rd, Rs, Rn SUBS Rd, Rs, Rn Subtract contents of Rn from contents of
Rs. Place result in Rd.
1 1 SUB Rd, Rs, #Offset3 SUBS Rd, Rs, #Offset3 Subtract 3-bit immediate value from
contents of Rs. Place result in Rd.