Samsung S3C2440A - Manual (Page 281)

S3C2440A RISC MICROPROCESSOR I/O PORTS
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GSTATUSn (General Status Registers)
Register Address R/W Description Reset Value
GSTATUS0 0x560000ac R External pin status Not define
GSTATUS1 0x560000b0 R/W Chip ID 0x32440001
GSTATUS2 0x560000b4 R/W Reset Status 0x1
GSTATUS3 0x560000b8 R/W Inform register 0x0
GSTATUS4 0x560000bc R/W Inform register 0x0
GSTATUS0 Bit Description
nWAIT [3] Status of nWAIT pin
NCON [2] Status of NCON pin
RnB [1] Status of RnB pin
BATT_FLT [0] Status of BATT_FLT pin
GSTATUS1 Bit Description
CHIP ID [0] ID register = 0x32440001
GSTATUS2 Bit Description
Reserved [3] Reserved
WDTRST [2] Boot is caused by Watch Dog Reset
cleared by writing “1”
SLEEPRST [1] Boot is caused by wakeup reset in sleep mode
cleared by writing “1”.
PWRST [0] Boot is caused by Power On Reset
cleared by writing “1”
GSTATUS3 Bit Description
inform [31:0] Inform register. This register is cleard by power on reset. Otherwise,
preserve data value.
GSTATUS4 Bit Description
inform [31:0] Inform register. This register is cleard by power on reset. Otherwise,
preserve data value.