Samsung S3C2440A - Manual (Page 126)

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET
4-5
FORMAT 1: MOVE SHIFTED REGISTER
15 0
0
14 10
[2:0] Destination Register
[5:3] Source Register
[10:6] Immediate Vale
[12:11] Opcode
0 = LSL
1 = LSR
2 = ASR
Offset5
6 5 3 2
Rd 0 0
13 12 11
Op Rs
Figure 4-2. Format 1
OPERATION
These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in
Table 4-2.
NOTE
All instructions in this group set the CPSR condition codes.
Table 4-2. Summary of Format 1 Instructions
OP THUMB Assembler ARM Equipment Action
00 LSL Rd, Rs, #Offset5 MOVS Rd, Rs, LSL #Offset5 Shift Rs left by a 5-bit immediate
value and store the result in Rd.
01 LSR Rd, Rs, #Offset5 MOVS Rd, Rs, LSR #Offset5 Perform logical shift right on Rs by a
5-bit immediate value and store the
result in Rd.
10 ASR Rd, Rs, #Offset5 MOVS Rd, Rs, ASR #Offset5 Perform arithmetic shift right on Rs
by a 5-bit immediate value and
store the result in Rd.