Samsung S3C2440A - Manual (Page 455)

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE
20-7
FLOWCHARTS OF OPERATIONS IN EACH MODE
The following steps must be executed before any IIC Tx/Rx operations.
1) Write own slave address on IICADD register, if needed.
2) Set IICCON register.
a) Enable interrupt
b) Define SCL period
3) Set IICSTAT to enable Serial Output
Write slave address to
IICDS.
Write 0xF0 (M/T Start)
to IICSTAT.
The data of the IICDS is
transmitted.
ACK period and then
interrupt is pending.
Write 0xD0 (M/T Stop)
to IICSTAT.
Write new data
transmitted to IICDS.
Stop?
Clear pending bit to
resume.
The data of the IICDS is
shifted to SDA.
START
Master Tx mode has
been configured.
Clear pending bit .
Wait until the stop
condition takes effect.
END
Y
N
Figure 20-6 Operations for Master/Transmitter Mode