Rainbow Electronics ATmega3290P_V - Manual (Page 60)

60
ATmega329/3210/649/6410
2552H–AVR–11/06
in “Alternate Port Functions” on page 65. Refer to the individual module sections for a
full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
Ports as General Digital
I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 24 shows a
functional description of one I/O-port pin, here generically called Pxn.
Figure 24. General Digital I/O (1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk
I/O
, SLEEP, and PUD are common to all ports.
Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O-Ports” on page 86, the DDxn bits are accessed at the
DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at
the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-
ured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when
reset condition becomes active, even if no clocks are running.
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q D
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
D
ATA
B
U
S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER