Rainbow Electronics ATmega3290P_V - Manual (Page 37)

37
ATmega329/3290/649/6490
2552H–AVR–11/06
ters (DIDR1 and DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” on page
202 and “DIDR0 – Digital Input Disable Register 0” on page 219 for details.
JTAG Interface and
On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power
down or Power save sleep mode, the main clock source remains enabled. In these
sleep modes, this will contribute significantly to the total current consumption. There are
three alternative ways to avoid this:
• Disable OCDEN Fuse.
• Disable JTAGEN Fuse.
• Write one to the JTD bit in MCUCSR.
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP
controller is not shifting data. If the hardware connected to the TDO pin does not pull up
the logic level, power consumption will increase. Note that the TDI pin for the next
device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit
in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the
JTAG interface.