Rainbow Electronics ATmega3290P_V - Manual (Page 230)

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ATmega329/3290/649/6490
2552H–AVR–11/06
LCDCRA – LCD Control and
Status Register A
• Bit 7 – LCDEN: LCD Enable
Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is
turned off immediately. Turning the LCD Controller/Driver off while driving a display,
enables ordinary port function, and DC voltage can be applied to the display if ports are
configured as output. It is recommended to drive output to ground if the LCD Control-
ler/Driver is disabled to discharge the display.
• Bit 6 – LCDAB: LCD Low Power Waveform
When LCDAB is written logic zero, the default waveform is output on the LCD pins.
When LCDAB is written logic one, the Low Power Waveform is output on the LCD pins.
If this bit is modified during display operation the change takes place at the beginning of
a new frame.
• Bit 5 – Res: Reserved Bit
This bit is reserved bit in the ATmega329/3290/649/6490 and will always read as zero.
• Bit 4 – LCDIF: LCD Interrupt Flag
This bit is set by hardware at the beginning of a new frame, at the same time as the dis-
play data is updated. The LCD Start of Frame Interrupt is executed if the LCDIE bit and
the I-bit in SREG are set. LCDIF is cleared by hardware when executing the corre-
sponding Interrupt Handling Vector. Alternatively, writing a logical one to the flag clears
LCDIF. Beware that if doing a Read-Modify-Write on LCDCRA, a pending interrupt can
be disabled. If Low Power Waveform is selected the Interrupt Flag is set every second
frame.
• Bit 3 – LCDIE: LCD Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the LCD Start of Frame Inter-
rupt is enabled.
• Bits 2:1 – Res: Reserved Bits
These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as
zero.
• Bit 0 – LCDBL: LCD Blanking
When this bit is written to one, the display will be blanked after completion of a frame. All
segment and common pins will be driven to ground.
LCDCRB – LCD Control and
Status Register B
Note: Bit 3, LCDPM3 is only available in ATmega3290/6490.
• Bit 7 – LCDCS: LCD Clock Select
When this bit is written to zero, the system clock is used. When this bit is written to one,
the external asynchronous clock source is used. The asynchronous clock source is
Bit 7 6 5 4 3 2 1 0
(0xE4) LCDEN LCDAB – LCDIF LCDIE – – LCDBL LCDCRA
Read/Write R/W R/W R R/W R/W R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0xE5) LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 LCDCRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Val-
ue 0 0 0 0 0 0 0 0