Switching time – Rainbow Electronics ATmega3290P_V User Manual

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ATmega329/3290/649/6490

2552H–AVR–11/06

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-
grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits
are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if
the selected clock source has a higher frequency than the maximum frequency of the
device at the present operating conditions. Note that any value can be written to the
CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating condi-
tions. The device is shipped with the CKDIV8 Fuse programmed.

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that
no glitches occur in the clock system and that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock fre-
quency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to
determine the state of the prescaler – even if it were readable, and the exact time it
takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2
before the new clock frequency is active. In this interval, 2 active clock edges are pro-
duced. Here, T1 is the previous clock period, and T2 is the period corresponding to the
new prescaler setting.

Table 13. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

128

256

Reserved