Rainbow Electronics ATmega3290P_V - Manual (Page 56)

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ATmega329/3290/649/6490
2552H–AVR–11/06
External Interrupt Mask
Register – EIMSK
• Bit 7 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 3 is enabled. Any change on any enabled PCINT30..24 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCINT3 Interrupt Vector. PCINT30..24 pins are enabled individually by
the PCMSK3 Register.
This bit is reserved bit in ATmega329/649 and should always be written to zero.
• Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCINT2 Interrupt Vector. PCINT23..16 pins are enabled individually by
the PCMSK2 Register.
This bit is reserved bit in ATmega329/649 and should always be written to zero.
• Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCINT1 Interrupt Vector. PCINT15..8 pins are enabled individually by the
PCMSK1 Register.
• Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCINT0 Interrupt Vector. PCINT7..0 pins are enabled individually by the
PCMSK0 Register.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the External Interrupt Control Register A (EICRA) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-
rupt Vector.
Bit 7 6 5 4 3 2 1 0
PCIE3 PCIE2 PCIE1 PCIE0 – – – INT0 EIMSK
Read/Write R/W R/W R/W R/W R R R R/W
Initial Value 0 0 0 0 0 0 0 0