Rainbow Electronics ATmega3290P_V - Manual (Page 221)

221
ATmega329/3290/649/6490
2552H–AVR–11/06
Figure 98. LCD Module Block Diagram
LCD Clock Sources The LCD Controller can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clk
LCD
is by default equal to the system clock, clk
I/O
.
When the LCDCS bit in the LCDCRB Register is written to logic one, the clock source is
taken from the TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC
voltage offset across LCD segments.
LCD Prescaler The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The
LCDPS2:0 bits selects clk
LCD
divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock
further by 1 to 8.
Output from the clock divider clk
LCD_PS
is used as clock source for the LCD timing.
LCD Memory The display memory is available through I/O Registers grouped for each common termi-
nal. When a bit in the display memory is written to one, the corresponding segment is
energized (on), and non-energized when a bit in the display memory is written to zero.
To energize a segment, an absolute voltage above a certain threshold must be applied.
This is done by letting the output voltage on corresponding COM pin and SEG pin have
opposite phase. For display with more than one common, one (1/2 bias) or two (1/3
bias) additional voltage levels must be applied. Otherwise, non-energized segments on
COM0 would be energized for all non-selected common.
Clock
Multiplexer
12-bit Prescaler
0
1
Divide by 1 to 8
LCD
Timing
LCDCRB
LCDFRR
clk
i/o
TOSC
LCDCRA
D
A
T
A
B
U
S
clk
LC
D
/4096
clk
LC
D
/2048
clk
LC
D
/128
clk
LC
D
/1024
clk
LC
D
/512
clk
LC
D
/256
clk
LC
D
/64
clk
LC
D
/16
Analog
Switch
Array
lcdcs
lcdcd2:0
lcdps2:0
clk
LCD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG35
SEG36
SEG37
SEG38
SEG39
COM0
COM1
COM2
COM3
LCD Buffer/
Driver
V
LCD
LCDDR 19 -15
LCDDR 14 -10
LCDDR 9 - 5
LCDDR 4 - 0
LATCH
array
LCD Ouput
Decoder
LCDCCR
lcdcc3:0
Contrast Controller/
Power Supply
clk
LCD_PS
LCD
CAP
40 x
4:1
MUX
LCD_voltage_ok
1/3 V
LCD
1/2 V
LCD
2/3 V
LCD
LCD Display Configuration
lcddc2:0