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Rainbow Electronics W90N740 User Manual

Page 97

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W90N740

Publication Release Date: November 26, 2004

- 93 -

Revision A4

MAC Missed Packet Count register (MPCNT_0, MPCNT_1)

The value in the MAC Missed Packet Count register (MPCNT) indicates the number of packets that were
discarded due to various types of errors. Together with status information on packets transmitted and
received, the MPCNT and these two pause count registers provide the information required for station
management.

Users can read the MPCNT to get current missed packet counter value and clears the register (read
clear). It is the responsibility of software to maintain a global count with more bits of precision.
However, users can write the MPCNT to set the initial value of counter overflow and start to count.
The counter overflow value ranges from 0x0000 to 0xFFFF (default value: 0x7FFF). It sets the
corresponding bit (MMP) in the MISTA and generates an interrupt if overflow is occurred and the
corresponding interrupt enable bit is set.

Register Address R/W

Description

Reset

Value

MPCNT_0 0xFFF0.3098 R/W Missed

Packet counter register

0x0000.7FFF

MPCNT_1 0xFFF0.3898 R/W Missed

Packet counter register

0x0000.7FFF

31

30

29

28

27

26

25

24

Reserved

23

22

21

20

19

18

17

16

Reserved

15

14

13

12

11

10

9

8

MPCNT

7

6

5

4

3

2

1

0

MPCNT


MPCNT [15:0]: MAC Missed Packet Count
Default value: 0x7FFF
It indicates the number of packets that were discarded due to various types of errors.
This counter indicates the following kinds of error:

Dribbling Bits error count (AECnt): The number of packets received with alignment errors. The

counter will be increment at the end of packet reception if the MISTA indicates the
alignment errors.

Frame discarded error count (RXFDCnt): The number of packets discarded by MAC because of

receive FIFO overflows, or because the RxON bit is cleared. This count does not include
the number of packets rejected by the CAM.

CRC error count (CECnt): The number of packets received with a CRC error. The counter will be

increment at the end of packet reception if the MISTA indicates the CRC errors.