Rainbow Electronics W90N740 - Manual (Page 73)

W90N740
Publication Release Date: November 26, 2004
- 69 - Revision A4
the ownership is granted to CPU.
If NATA is enabled, NATA is also allowed to access current descriptor and bit 30 is set to 1 by NATA
when NATA is processing.
7.5.1.2 Rx Status: Receive Status
This field is updated by EMC after reception completed. The detail description is on next page.
Frame Length: Received Frame Length
This field is the size of the received frame.
Data Buffer Starting Address
This field is the starting address of the frame data to be received.
Next Descriptor Start Address
This field is the start address of the next frame descriptor.
7.5.1.3 NAT Information
This field is reserved for MAC Rx to send information for NAT processing. For user driver program, it
is forbidden to modify these bits.
Rx Status (RXSTA): Receive Status
29 28 27 26 25 24
Hit IPHit PortHit Inverse NATFSH Nop
23 22 21 20 19 18 17 16
Reserved RP ALIE RXGD PTLE Reserved CRCE RXINTR
Bits 29-24 are NAT information for the NAT accelerator, and reserved if the NATA is disabled.
Hit: current packet is hit with NAT entry table
The value is 1 if current packet IP/port is in the entry list. If NATA is disabled, the bit is reserved.
7.5.1.4 IPHit: current packet is hit on IP address
The value is 1 if current packet IP/port is hit in the IP address location.
PortHit: current packet is hit on Port Number
The value is 1 if current packet IP/port is hit in the port number location.
Inverse: current hit entry is setting on inverse mode
The value is 1 if current hit entry is on inverse mode.