Rainbow Electronics W90N740 - Manual (Page 90)

W90N740
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EnRXGD [4]: Enable Receive Good interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if a packet was successfully received with no
errors.
EnPTLE [3]: Enable Packet Too Long interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the MAC received a frame longer than 1518
bytes (unless ALP in MCMDR is set).
EnRXOV [2]: Enable Receive FIFO Overflow interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the MAC receives FIFO was full when receiving a
frame.
EnCRCE [1]: Enable CRC Error interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the CRC at the end of a packet is not correct, or
else the PHY asserted Rx_er during packet reception.
EnRXINTR [0]: Enable Interrupt on Receive interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the reception of a packet caused an interrupt to
be generated. This includes a good received interrupt, if the EnRXGD bit is set.