Rainbow Electronics W90N740 User Manual
Page 70
W90N740
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Cache Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
z
Flush I-Cache and D-Cache
z
Load and lock I-Cache and D-Cache
z
Unlock I-Cache and D-Cache
z
Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
Register Address R/W
Description
Reset
Value
CAHCON
0xFFF0.2004
R/W Cache control register
0x0000.0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
DRWB ULKS ULKA LDLK FLHS FLHA DCAH ICAH
DRWB [7] ：Drain write buffer
Forces write buffer data to be written to main memory.
ULKS [6] ：Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be
specified.
ULKA [5] ：Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared to 0.
LDLK [4] ：Load and Lock I-Cache/D-Cache
Loads the instruction or data from external memory and locks into cache. Both WAY and ADDR bits in
CAHADR register must be specified.
FLHS [3] ：Flush I-Cache/D-Cache single line
Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be
specified.
FLHA [2] ：Flush I-Cache/D-Cache entirely