Rainbow Electronics W90N740 - Manual (Page 24)

W90N740
- 20 -
Table 7.2.3 and Table 7.2.4
Using big-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0, 4, 8, C
X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table7.2.3 Word access write operation with Big Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD 31 0
ABCD 31 0
ABCD
SA WA WA WA
Bit Number
SD
31 0
ABCD 31 0
AB CD 31 0
A B C D
Bit Number
ED
31 0
ABCD 15 0
AB
15 0
CD
7 0
A
7 0
B
7 0
C
7 0
D
XA WA WA WA+2 WA WA+1 WA+2 WA+3
nWBE [3-0] /
SDQM [3-0]
AAAA XXAA XXAA XXXA XXXA XXXA XXXA
Bit Number
XD
31 0
ABCD 15 0
AB
15 0
CD
7 0
A
7 0
B
7 0
C
7 0
D
Bit Number
Ext. Mem Data
31 0
ABCD 15 0
AB
15 0
CD
7 0
A
7 0
B
7 0
C
7 0
D
Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write
Table7.2.4 Word access read operation with Big Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD 31 0
CDAB 31 0
DCBA
SA WA WA WA
Bit Number
SD
31 0
ABCD 31 0
CD AB 31 0
D C B A
Bit Number
ED
31 0
ABCD 31 0
CD XX 31 0
CD AB 31 0
D X X X
31 0
D C X X
31 0
D C B X
31 0
D C B A
XA WA WA WA+2 WA WA+1 WA+2 WA+3
SDQM [3-0] AAAA XXAA XXAA XXXA XXXA XXXA XXXA
Bit Number
XD
31 0
ABCD 15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Bit Number
Ext. Mem Data
31 0
ABCD 15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Timing Sequence 1st read 2nd read 1st read 2nd read 3rd read 4th read