Rainbow Electronics W90N740 User Manual

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W90N740

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7.5 Ethernet MAC Controller (EMC)

The W90N740 has two Ethernet MAC Controllers (EMC) for WAN/LAN application. Each EMC has its
DMA controller, transmit FIFO, and receive FIFO. The Ethernet MAC controller consists of IEEE
802.3/Ethernet protocol engine with internal CAM address register for entry address comparison,
Transmit-FIFO, Receive-FIFO, TX/RX state machine controller and status controller. The EMC
supplies selectable MII (Media Independent Interface) or RMII (Reduced MII), for 10/100Mbits/s PHY
operated with 25M/2.5M Hz TXCLK/RXCLK.

The Features of each EMC:

• IEEE 802.3 protocol engine with programmable MII or RMII interface for 10/100 Mbits/s
• DMA engine with burst mode
• 256 bytes transmit & 256 bytes receive FIFO for MAC protocol engine and DMA access
• Built-in 16 entry CAM Address Register
• Support long frame (more than 1518 bytes) and short frame (less than 64 bytes)
• Re-transmit (during collision) the frame without DMA access
• Half or full duplex function option
• Support Station Management for external PHY
• On-Chip Pad generation

7.5.1 EMC Descriptors

Buffer descriptors are used to handle the control, status and data information of each
received/transmitted frame. There is much information contained in the descriptors. The W90N740
totally implements four registers for receiving and four registers for transmitting, respectively. All the
registers are described below.

7.5.1.1 Rx Buffer Descriptor (RXBD)

3
1

3
0

2
9

1
6

1
5

Rx Status

Frame Length

Data Buffer Starting Address

NAT Information (Reserved)

Next Descriptor Starting Address

O: Ownership bits

BIT [31: 30]

= CPU

= DMA

11 =

NATA

= Undefined

W90N740 EMC receive DMA is allowed to access current descriptor if bit 31 is set to 1 by the user
driver program. If the entire frame is received successfully, then the ownership bit 31 is cleared and