Rainbow Electronics W90N740 - Manual (Page 52)

W90N740
- 48 -
LATENCY [12:11] ：The CAS Latency of SDRAM bank 0/1
Defines the CAS latency of external SDRAM bank 0/1
LATENCY [12:11] MCLK
0 0 1
0 1 2
1 0 3
1 1 REVERSED
COMPBK [7] ： Number of component bank in SDRAM bank 0/1
Indicates the number of component bank (2 or 4 banks) in external SDRAM bank 0/1.
0 = 2 banks
1 = 4 banks
DBWD [6:5] ：Data bus width for SDRAM bank 0/1
Indicates the external data bus width connect with SDRAM bank 0/1
If DBWD = 00, the assigned SDRAM access signal is not generated i.e. disable.
DBWD [6:5] Bits
0 0 Bank disable
0 1 8-bit (byte)
1 0 16-bit (half-word)
1 1 32-bit (word)
COLUMN [4:3] ：Number of column address bits in SDRAM bank 0/1
Indicates the number of column address bits in external SDRAM bank 0/1.
COLUMN [4:3] Bits
0 0 8
0 1 9
1 0 10
1 1 REVERSED