Rainbow Electronics W90N740 - Manual (Page 19)

W90N740
Publication Release Date: November 26, 2004
- 15 - Revision A4
7.2 System Manager
7.2.1 Overview
The functions of the System Manager:
• System memory map & on-chip peripherals memory map
• The data bus width of external memory address & data bus connection with external memory
• Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode
• Power-On setting
• On-Chip PLL module control & Clock select control
7.2.2 System Memory Map
W90N740 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The
On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0.0000 – 0xFFFF.FFFF) and the On-
Chip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable
space: 0x0~0x7FDF.FFFF if Cache ON; non-cacheable space: 0x8000.0000 ~ 0xFFDF.FFFF).
The size and location of each bank is determined by the register settings for “current bank base address
pointer” and “current bank size”. (*Note: The address boundaries of consecutive banks must not overlap,
when setting the bank control registers.)
The start address of each memory bank is not fixed, except On-Chip Peripherals and On-Chip RAM. You
can use bank control registers to assign a specific bank start address by setting the bank’s base pointer
(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<
18” and the bank’s size is “current bank size”.
In the event of an access request to an address outside any programmed bank size, an abort signal is
generated. The maximum accessible memory size of each external IO bank is 32M bytes, and 64M
bytes on SDRAM banks.