Rainbow Electronics W90N740 User Manual
Page 137
W90N740
Publication Release Date: November 26, 2004
- 133 -
Revision A4
Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1)
The GDMA channel starts reading its data from the source address as defined in this source base
address register.
Register Address
R/W
Description
Reset
Value
GDMA_SRCB0 0xFFF0.4004 R/W Channel 0 Source Base Address Register
0x0000.0000
GDMA_SRCB1 0xFFF0.4024 R/W Channel 1 Source Base Address Register
0x0000.0000
31
30
29
28
27
26
25
24
SRC_BASE_ADDR [31:24]
23
22
21
20
19
18
17
16
SRC_BASE_ADDR [23:16]
15
14
13
12
11
10
9
8
SRC_BASE_ADDR [15:8]
7
6
5
4
3
2
1
0
SRC_BASE_ADDR [7:0]
SRC_BASE_ADDR [31:0]: 32-bit Source Base Address
Channel 0/1 Destination Base Address Register (GDMA_DSTB0, GDMA_DSTB1)
The GDMA channel starts writing its data to the destination address as defined in this destination base
address register. During a block transfer, the GDMA determines successive destination addresses by
adding to or subtracting from the destination base address.
Register Address
R/W
Description
Reset
Value
GDMA_DSTB0 0xFFF0.4008 R/W Channel 0 Destination Base Address Register
0x0000.0000
GDMA_DSTB1 0xFFF0.4028 R/W Channel 1 Destination Base Address Register
0x0000.0000
31
30
29
28
27
26
25
24
DST_BASE_ADDR [31:24]
23
22
21
20
19
18
17
16
DST_BASE_ADDR [23:16]
15
14
13
12
11
10
9
8
DST_BASE_ADDR [15:8]
7
6
5
4
3
2
1
0
DST_BASE_ADDR [7:0]
DST_BASE_ADDR [31:0]: 32-bit Destination Base Address