Rainbow Electronics W90N740 - Manual (Page 163)

W90N740
Publication Release Date: November 26, 2004
- 159 - Revision A4
FIFO Control Register (FCR)
Register Address R/W Description Reset Value
FCR 0xFFF8.0008 W FIFO Control Register Undefined
7 6 5 4 3 2 1 0
RFITL RESERVED DMS TFR RFR FME
RFITL [7:6]: RX FIFO Interrupt (Irpt_RDA) Trigger Level
RFITL [7:6] Irpt_RDA Trigger Level (Bytes)
00 01
01 04
10 08
11 14
DMS [3]: DMA Mode Select
The DMA function is not implemented in this version.
TFR [2]: TX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty
(TX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is
generated.
RFR [1]: RX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The RX FIFO becomes
empty (RX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset
pulse is generated.
FME [0]: FIFO Mode Enable
Because UART is always operating in the FIFO mode, writing this bit has no effect while reading
always gets logical one. This bit must be 1 when other FCR bits are written to; otherwise, they will not
be programmed.