Rainbow Electronics W90N740 - Manual (Page 25)

W90N740
Publication Release Date: November 26, 2004
- 21 - Revision A4
Table 7.2.5 and Table 7.2.6
Using big-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0, 2, 4, 6, 8, A, C, E
HAL = Address whose LSB is 0, 4, 8, C
HAU = Address whose LSB is 2, 6, A, E X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table7.2.5 Half-word access write operation with Big Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD 31 0
ABCD 31 0
ABCD
SA HAL HAU HA HA
Bit Number
SD
31 0
CD CD
31 0
CD CD
31 0
CD CD
31 0
CD CD
31 0
CD CD
Bit Number
ED
31 0
CD CD
31 0
CD CD
31 0
CD CD
7 0
C
7 0
D
XA HAL HAL HA HA HA+1
nWBE [3-0] /
SDQM [3-0]
AAUU UUAA XXAA XXXA XXXA
Bit Number
XD
31 0
CD CD
31 0
CD CD
15 0
CD
7 0
C
7 0
D
Bit Number
Ext. Mem Data
31 16
CD
15 0
CD
15 0
CD
7 0
C
7 0
D
Timing Sequence 1st write 2nd write
Table7.2.6 Half-word access read operation with Big Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
15 0
AB
15 0
CD
15 0
CD
15 0
DC
SA HAL HAU HA HA
Bit Number
SD
15 0
AB
15 0
CD
15 0
CD
15 0
DC
Bit Number
ED
15 0
AB
15 0
CD
15 0
CD
15 0
DX
15 0
DC
XA HAL HAL HA HA HA+1
SDQM [3-0] AAUU UUAA XXAA XXXA XXXA
Bit Number
XD
31 0
AB CD
31 0
AB CD
15 0
CD
7 0
D
7 0
C
Bit Number
Ext. Mem Data
31 0
ABCD 15 0
CD
7 0
D
7 0
C
Timing Sequence 1st read 2nd read