Rainbow Electronics W90N740 - Manual (Page 16)

W90N740
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Pins Description, continued
PIN NAME
IO
TYPE
PAD
TYPE
DESCRIPTION
Ethernet Interface (1)
MDC1 O -
MII Management Data Clock for Ethernet 1. It is the reference clock of MDIO1.
Each MDIO1 data will be latched at the rising edge of MDC1 clock.
MDIO1 IO -
MII Management Data I/O for Ethernet 1. It is used to transfer MII control and
status information between PHY and MAC.
COL1 I -
Collision Detect for Ethernet 1 in MII mode. This shall be asserted by PHY upon
detecting a collision happened over the medium. It will be asserted and lasted
until collision condition vanishes. External pull-up is necessary in RMII mode.
CRS1 I -
Carrier Sense for Ethernet 1 in MII mode. External pull-up is necessary in RMII
mode.
TX1_CLK I -
Transmit Data Clock for Ethernet 1 in MII mode, TX1_CLK is driven by PHY and
provides the timing reference for TX1_EN and TX1D. The clock will be 25MHz or
2.5 MHz. External pull-up will be necessary in RMII mode.
TX1D [3:0] /
--,R1A_TXD [1:0]
O -
Transmit Data bus (4-bit) for Ethernet 1 in MII mode. The nibble transmit data
bus is synchronized with TX1_CLK. It should be latched by PHY at the rising
edge of TX1_CLK.
In RMII mode, TX1D [1:0] are used as R1A_TXD [1:0], 2-bit Transmit Data bus
for Ethernet 1
TX1_EN/
R1A_TXEN/R1B_TXEN
O -
Transmit Enable for Ethernet 1 in MII and RMII mode. It indicates the transmit
activity to external PHY. It will be synchronized with TX1_CLK in MII mode.
RX1_CLK /
R1A_REFCLK
I -
Receive Data Clock for Ethernet 1 in MII mode. When it is used as a received
clock pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The
minimum duty cycle at its high or low state should be 35% of the nominal period
for all conditions.
In RMII mode, this pin is used as R1A_REFCLK, Reference Clock and only
available for 176-pin package. The clock shall be 50MHz +/-50 ppm with
minimum 35% duty cycle at high or low state.
RX1D [3:0] /
--, R1A_RXD[1:0]
I -
Receive Data bus (4-bit) for Ethernet 1 in MII mode. They are driven by external
PHY, and should be synchronized with RX1_CLK and valid only when RX1_DV
is valid.
In RMII mode, RX1D [1:0] are used as R1A_RXD [1:0], 2-bit Receive Data bus
for Ethernet 1.
RX1_DV/
R1A_CRSDV
I -
Receive Data Valid for Ethernet 1 in MII mode. It will be asserted when received
data is coming and present, and de-asserted at the end of the frame.
In RMII mode, this pin is used as the R1A_CRSDV, Carrier Sense / Receive
Data Valid for Ethernet 1 and only available for 176-pin package. The
R1A_CRSDV shall be asserted by PHY when the receive medium is non-idle.
Loss of carrier shall result in the de-assertion of R1A_CRSDV synchronous to
the cycle of R1A_REFCLK, and only on nibble boundaries.
RX1_ERR /
R1A_RXERR
I -
Receive Data Error for Ethernet 1 in MII and RMII mode. It indicates a data error
detected by PHY. The assertion should be lasted for longer than a period of
RX0_CLK. When RX0_ERR is asserted, the MAC will report a CRC error.