Rainbow Electronics W90N740 - Manual (Page 108)

W90N740
- 104 -
Default value: 0
This bit is set if a packet was successfully received with no errors.
PTLE [3]: Packet Too Long Error
Default value: 0
This bit is set if the MAC received a frame longer than 1518 bytes (unless ALP in MCMDR is set).
RXOV [2]: Receive FIFO Overflow error
Default value: 0
This bit is set if the MAC receives FIFO was overflow when receiving a frame.
CRCE [1]: CRC Error
Default value: 0
This bit is set if the CRC at the end of a packet is not correct, or else the PHY asserted Rx_er during
packet reception.
RXINTR [0]: Interrupt on Receive
Default value: 0
This bit is set if the reception of a packet caused an interrupt to be generated. This includes a good
received interrupt, if the EnRXGD bit in MIEN is set.