Rainbow Electronics W90N740 User Manual
Page 35
W90N740
Publication Release Date: November 26, 2004
- 31 -
Revision A4
PLL Control Register （PLLCON）
W90N740 provides two options for clock generation - crystal and oscillator.
The external clock via EXTAL input pin as the reference clock input of PLL module. The external clock
can bypass the PLL and be used to the internal system clock by pull-down the data D15 pin. Using
PLL’s output clock for the internal system clock, D15 pin must be pull-up.
Register Address
R/W
Description
Reset
Value
PLLCON
0xFFF0.0008 R/W PLL Control Register
0x0000.2F01
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED PWDEN
15
14
13
12
11
10
9
8
FBDV
7
6
5
4
3
2
1
0
FBDV OTDV
INDV
PWDEN [16] ：Power down mode enable
0 = PLL is in normal mode (default)
1 = PLL is in power down mode
FBDV [15:7] ：PLL VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL.
OTDV [6:5] ：PLL output clock divider
OTDV [6:5]
Divided by
0 0
1
0 1
2
1 0
2
1 1
4