Rainbow Electronics W90N740 User Manual
Page 110
W90N740
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RXHA [1]: Reception Halted
Default value: 0
This bit is set if reception is halted by clearing RXON bit in the MAC Command Register (MCMDR).
CFR [0]: Control Frame Received
Default value: 0
This bit is set if (1) the packet received is a MAC control frame (type = 8808H), (2) if the CAM
recognizes the packet address, and (3) if the frame length is 64 bytes.
MAC Received Pause Count Register (MRPC_0, MRPC_1)
The received pause count register, MRPC, stores the value of the 16-bit received pause counter. It is
read only.
Register Address R/W
Description
Reset
Value
MRPC_0 0xFFF0.30BC R MAC
Receive
Pause count register
0x0000.0000
MRPC_1 0xFFF0.38BC R MAC
Receive
Pause count register
0x0000.0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
MRPC
7
6
5
4
3
2
1
0
MRPC
MRPC [15:0]: MAC Received Pause Count Register
Default value: 0
The count value indicates the number of time slots the transmitter was paused due to the receipt of
control pause operation packets from the MAC.