Rainbow Electronics W90N740 - Manual (Page 89)

W90N740
Publication Release Date: November 26, 2004
- 85 - Revision A4
Set this bit to enable the interrupt, which is generated if there is no error during NATA do the NAT
processing.
EnRxBErr [11]: Enable Receive Bus ERROR interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if system bus access error from Rx to system
memory occurred. If the interrupt is triggered, the Rx state machine will stay at Halt state. The software
reset is recommended while this interrupt occurred.
EnRDU [10]: Enable Receive Descriptor Unavailable interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if receive descriptors owned to the RxDMA is
unavailable. That means, if the RxDMA finds the ownership of descriptors is not belonged to RxDMA, it
will generate an interrupt and Rx operation will be ceased till the user issues a write command to
Receive Start Demand register to restart the Rx operation.
EnDEN [9]: Enable DMA early notification interrupts
Default value: 0
Set this bit to enable the interrupt, when the length field of the current frame is received.
EnDFO [8]: Enable DMA receive frame over maximum size interrupt
Default value: 0
Set this bit to enable the interrupt, when the received frame size is larger than the value stored in
RXMS.
EnMMP [7]: Enable More Missed Packets interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated when the missed error counter rolls over.
EnRP [6]: Enable Runt Packet on Receive interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the MAC receives a frame shorter less than 64
bytes.
EnALIE [5]: Enable Alignment Error interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the frame length in bits was not a multiple of
eight.