Rainbow Electronics W90N740 User Manual

Page 162

W90N740

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Interrupt Identification Register (IIR)

Register Address R/W

Description

Reset

Value

IIR

0xFFF8.0008

Interrupt Identification Register

0x8181.8181

FMES RFTLS DMS

IID

NIP

FMES [7]: FIFO Mode Enable Status

This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enable,
this bit always shows the logical 1 when CPU is reading this register.

RFTLS [6:5]: RX FIFO Threshold Level Status

These bits show the current setting of receiver FIFO threshold level (RTHO). The meaning of RTHO is
defined in the following FCR description.

DMS [4]: DMA Mode Select

The DMA function is not implemented in this version. When reading IIR, the DMS is always returned
0.

IID [3:1]: Interrupt Identification

The IID together with NIP indicates the current interrupt request from UART.

NIP [0]: No Interrupt Pending

There is no pending interrupt.

Table 7.9.1 Interrupt Control Functions

IIR [3:0]

Priority

Interrupt Type

Interrupt Source

Interrupt Reset control

- - - 1

None

0110 Highest

Receiver Line Status

(Irpt_RLS)

Overrun error, parity error, framing
error, or break interrupt

Reading the LSR

0100 Second

Received Data

Available (Irpt_RDA)

Receiver FIFO threshold level is
reached

Receiver FIFO drops below
the threshold level

1100 Second

Receiver FIFO Time-

out (Irpt_TOUT)

Receiver FIFO is non-empty and
no activities are occurred in the
receiver FIFO during the TOR
defined time duration

Reading the RBR

0010 Third

Transmitter Holing

(Irpt_THRE)

Transmitter holding register empty

Reading the IIR (if source of
interrupt is Irpt_THRE) or
writing into the THR

0000 Fourth

MODEM Status

(Irpt_MOS)

The CTS, DSR, or DCD bits are
changing state or the RI bit is
changing from high to low.

Reading the MSR

Note: These definitions of bit 7, bit 6, bit 5, bit 4 are different from the 16550.