Rainbow Electronics W90N740 User Manual
Page 166
W90N740
- 162 -
Line Status Control Register (LSR)
Register Address R/W
Description
Reset
Value
LSR
0xFFF8.0014
R
Line Status Register
0x6060.6060
7
6
5
4
3
2
1
0
ERR_RX TE THRE BII FEI PEI OEI RFDR
ERR_RX [7]: RX FIFO Error
0 = RX FIFO works normally
1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO.
ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO.
TE [6]: Transmitter Empty
0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register (TSR) are not
empty.
1 = Both THR and TSR are empty.
THRE [5]: Transmitter Holding Register Empty
0 = THRE is not empty.
1 = THRE is empty.
THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The
CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an
interrupt (Irpt_THRE) to the CPU when IER [1]=1.
BII [4]: Break Interrupt Indicator
This bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for
longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits)
and is reset whenever the CPU reads the contents of the LSR.
FEI [3]: Framing Error Indicator
This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop
bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads
the contents of the LSR.